Simulation of a tripled majority voter by Quartus Prime State Machine
DOI:
https://doi.org/10.17072/1993-0550-2021-1-57-60Keywords:
Quartus Prime, VHDL, triple majority element, LUT FPGA, State Machine Editor, Map ViewerAbstract
A triple majority element based on a full adder in the Quartus Prime State Machine is investigated to create highly reliable FPGA-based digital automata. For this purpose, two new groups of inputs are added to the previously developed automaton graph. Modeling the failure of one of the three majorities is performed by specifying the corresponding constant in one of the three input groups. The performance indicators of the developed device are evaluated.References
Intel Quartus Prime Pro Edition Help version 20.3 > enum_encoding VHDL Synthesis Attribute. Available at: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vhdl/vhdl_file_dir_enum_encoding.htm (Accessed 20 November 2020).
Тюрин С.Ф. Надежность систем автоматизации: учеб. пособие. Перм. нац. исслед. политехн. ун-т. Пермь: Изд-во ПНИПУ, 2012. 262 с.
Grekov A.V., Tyurin S.F. Throughput Logic Simulation by Quartus Prime State Machine. Proceedings of the 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, ElConRus 2020-January. P. 127–129. DOI: 10.1109/EIConRus49466.2020.9039474.
Тюрин С.Ф., Греков А.В., Громов О.А. Реализация цифровых автоматов в системе Quartus фирмы Altera: учеб. пособие. Пермь: Изд-во Перм. гос. техн. ун-та, 2011. 134 с.
Тюрин С.Ф. Анализ настроек логических элементов при проектировании конечного автомата в системе QUARTUS II // Наука и технологические разработки. 2015. Т. 94, № 2. С. 17–27.
Downloads
Published
How to Cite
Issue
Section
License
Articles are published under license Creative Commons Attribution 4.0 International (CC BY 4.0).
